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<div class="header">
  <div class="headertitle"><div class="title">TIM Exported Types <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m.html">TIM</a></div></div></div>
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<tr class="heading"><td colspan="2"><h2 id="header-nested-classes" class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:TIM_5FBase_5FInitTypeDef" id="r_TIM_5FBase_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___base___init_type_def.html">TIM_Base_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Time base Configuration Structure definition.  <a href="struct_t_i_m___base___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FOC_5FInitTypeDef" id="r_TIM_5FOC_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___o_c___init_type_def.html">TIM_OC_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Output Compare Configuration Structure definition.  <a href="struct_t_i_m___o_c___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FOnePulse_5FInitTypeDef" id="r_TIM_5FOnePulse_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___one_pulse___init_type_def.html">TIM_OnePulse_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM One Pulse Mode Configuration Structure definition.  <a href="struct_t_i_m___one_pulse___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FIC_5FInitTypeDef" id="r_TIM_5FIC_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___i_c___init_type_def.html">TIM_IC_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Input Capture Configuration Structure definition.  <a href="struct_t_i_m___i_c___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FEncoder_5FInitTypeDef" id="r_TIM_5FEncoder_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___encoder___init_type_def.html">TIM_Encoder_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Encoder Configuration Structure definition.  <a href="struct_t_i_m___encoder___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FClockConfigTypeDef" id="r_TIM_5FClockConfigTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___clock_config_type_def.html">TIM_ClockConfigTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Configuration Handle Structure definition.  <a href="struct_t_i_m___clock_config_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FClearInputConfigTypeDef" id="r_TIM_5FClearInputConfigTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___clear_input_config_type_def.html">TIM_ClearInputConfigTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Clear Input Configuration Handle Structure definition.  <a href="struct_t_i_m___clear_input_config_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FMasterConfigTypeDef" id="r_TIM_5FMasterConfigTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___master_config_type_def.html">TIM_MasterConfigTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Master configuration Structure definition.  <a href="struct_t_i_m___master_config_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FSlaveConfigTypeDef" id="r_TIM_5FSlaveConfigTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___slave_config_type_def.html">TIM_SlaveConfigTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Slave configuration Structure definition.  <a href="struct_t_i_m___slave_config_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FBreakDeadTimeConfigTypeDef" id="r_TIM_5FBreakDeadTimeConfigTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___break_dead_time_config_type_def.html">TIM_BreakDeadTimeConfigTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Break input(s) and Dead time configuration Structure definition.  <a href="struct_t_i_m___break_dead_time_config_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FHandleTypeDef" id="r_TIM_5FHandleTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___handle_type_def.html">TIM_HandleTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Time Base Handle Structure definition.  <a href="struct_t_i_m___handle_type_def.html#details">More...</a><br /></td></tr>
</table><table class="memberdecls">
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Enumerations</h2></td></tr>
<tr class="memitem:gae0994cf5970e56ca4903e9151f40010c" id="r_gae0994cf5970e56ca4903e9151f40010c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae0994cf5970e56ca4903e9151f40010c">HAL_TIM_StateTypeDef</a> { <br />
&#160;&#160;<a class="el" href="#ggae0994cf5970e56ca4903e9151f40010ca28011b79e60b74a6c55947c505c51cbc">HAL_TIM_STATE_RESET</a> = 0x00U
, <a class="el" href="#ggae0994cf5970e56ca4903e9151f40010ca4545554d7fa04d17e78d69d17cb7e4b3">HAL_TIM_STATE_READY</a> = 0x01U
, <a class="el" href="#ggae0994cf5970e56ca4903e9151f40010ca1ddbfef19ad0562eb8143919b710cc12">HAL_TIM_STATE_BUSY</a> = 0x02U
, <a class="el" href="#ggae0994cf5970e56ca4903e9151f40010ca03e3339df71a74ac37820f72c2989371">HAL_TIM_STATE_TIMEOUT</a> = 0x03U
, <br />
&#160;&#160;<a class="el" href="#ggae0994cf5970e56ca4903e9151f40010ca318cceb243cb9ca9e01833913e4f90ea">HAL_TIM_STATE_ERROR</a> = 0x04U
<br />
 }</td></tr>
<tr class="memdesc:gae0994cf5970e56ca4903e9151f40010c"><td class="mdescLeft">&#160;</td><td class="mdescRight">HAL State structures definition.  <a href="#gae0994cf5970e56ca4903e9151f40010c">More...</a><br /></td></tr>
<tr class="memitem:ga1a70fcbe9952e18af5c890e216a15f34" id="r_ga1a70fcbe9952e18af5c890e216a15f34"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1a70fcbe9952e18af5c890e216a15f34">HAL_TIM_ChannelStateTypeDef</a> { <a class="el" href="#gga1a70fcbe9952e18af5c890e216a15f34a430f7e41a278868bc1a7c5de6a08dc94">HAL_TIM_CHANNEL_STATE_RESET</a> = 0x00U
, <a class="el" href="#gga1a70fcbe9952e18af5c890e216a15f34a38f4c5665247f7c997d0b200ed7ccc0e">HAL_TIM_CHANNEL_STATE_READY</a> = 0x01U
, <a class="el" href="#gga1a70fcbe9952e18af5c890e216a15f34ad5dca7086716ee2cde9aaccaefd838ff">HAL_TIM_CHANNEL_STATE_BUSY</a> = 0x02U
 }</td></tr>
<tr class="memdesc:ga1a70fcbe9952e18af5c890e216a15f34"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM Channel States definition.  <a href="#ga1a70fcbe9952e18af5c890e216a15f34">More...</a><br /></td></tr>
<tr class="memitem:ga9b87df539778a60ea940a9d5ba793f7c" id="r_ga9b87df539778a60ea940a9d5ba793f7c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9b87df539778a60ea940a9d5ba793f7c">HAL_TIM_DMABurstStateTypeDef</a> { <a class="el" href="#gga9b87df539778a60ea940a9d5ba793f7ca98c26cb59bb0c07b7f020d7ff8678bb8">HAL_DMA_BURST_STATE_RESET</a> = 0x00U
, <a class="el" href="#gga9b87df539778a60ea940a9d5ba793f7ca44e8b59c22cd2b17d449b120e03e4952">HAL_DMA_BURST_STATE_READY</a> = 0x01U
, <a class="el" href="#gga9b87df539778a60ea940a9d5ba793f7ca2de45462aabea1ed8b0d249441404e82">HAL_DMA_BURST_STATE_BUSY</a> = 0x02U
 }</td></tr>
<tr class="memdesc:ga9b87df539778a60ea940a9d5ba793f7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Burst States definition.  <a href="#ga9b87df539778a60ea940a9d5ba793f7c">More...</a><br /></td></tr>
<tr class="memitem:gaa3fa7bcbb4707f1151ccfc90a8cf9706" id="r_gaa3fa7bcbb4707f1151ccfc90a8cf9706"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa3fa7bcbb4707f1151ccfc90a8cf9706">HAL_TIM_ActiveChannel</a> { <br />
&#160;&#160;<a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706a2024e95c48b58ec9b2115faa276e3fad">HAL_TIM_ACTIVE_CHANNEL_1</a> = 0x01U
, <a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706ae80e6a1dd1c479f504219c0fec2f3322">HAL_TIM_ACTIVE_CHANNEL_2</a> = 0x02U
, <a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706acc3fcf4ee6d91744c4bc6a5eccde2601">HAL_TIM_ACTIVE_CHANNEL_3</a> = 0x04U
, <a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706a7d98ec7e385cacb3aaa6cec601fa6ab6">HAL_TIM_ACTIVE_CHANNEL_4</a> = 0x08U
, <br />
&#160;&#160;<a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706a50b9b4be055407e9f566d8da0a7e07cc">HAL_TIM_ACTIVE_CHANNEL_5</a> = 0x10U
, <a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706a368a574b486286c87f763957a0ef9d93">HAL_TIM_ACTIVE_CHANNEL_6</a> = 0x20U
, <a class="el" href="#ggaa3fa7bcbb4707f1151ccfc90a8cf9706a574f72ac3bb41fe660318aa42dfdc98d">HAL_TIM_ACTIVE_CHANNEL_CLEARED</a> = 0x00U
<br />
 }</td></tr>
<tr class="memdesc:gaa3fa7bcbb4707f1151ccfc90a8cf9706"><td class="mdescLeft">&#160;</td><td class="mdescRight">HAL Active channel structures definition.  <a href="#gaa3fa7bcbb4707f1151ccfc90a8cf9706">More...</a><br /></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-enum-members" id="doc-enum-members"></a><h2 id="header-doc-enum-members" class="groupheader">Enumeration Type Documentation</h2>
<a id="gaa3fa7bcbb4707f1151ccfc90a8cf9706" name="gaa3fa7bcbb4707f1151ccfc90a8cf9706"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa3fa7bcbb4707f1151ccfc90a8cf9706">&#9670;&#160;</a></span>HAL_TIM_ActiveChannel</h2>

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          <td class="memname">enum <a class="el" href="#gaa3fa7bcbb4707f1151ccfc90a8cf9706">HAL_TIM_ActiveChannel</a></td>
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</div><div class="memdoc">

<p>HAL Active channel structures definition. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a2024e95c48b58ec9b2115faa276e3fad" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a2024e95c48b58ec9b2115faa276e3fad"></a>HAL_TIM_ACTIVE_CHANNEL_1&#160;</td><td class="fielddoc"><p>The active channel is 1 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706ae80e6a1dd1c479f504219c0fec2f3322" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706ae80e6a1dd1c479f504219c0fec2f3322"></a>HAL_TIM_ACTIVE_CHANNEL_2&#160;</td><td class="fielddoc"><p>The active channel is 2 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706acc3fcf4ee6d91744c4bc6a5eccde2601" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706acc3fcf4ee6d91744c4bc6a5eccde2601"></a>HAL_TIM_ACTIVE_CHANNEL_3&#160;</td><td class="fielddoc"><p>The active channel is 3 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a7d98ec7e385cacb3aaa6cec601fa6ab6" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a7d98ec7e385cacb3aaa6cec601fa6ab6"></a>HAL_TIM_ACTIVE_CHANNEL_4&#160;</td><td class="fielddoc"><p>The active channel is 4 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a50b9b4be055407e9f566d8da0a7e07cc" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a50b9b4be055407e9f566d8da0a7e07cc"></a>HAL_TIM_ACTIVE_CHANNEL_5&#160;</td><td class="fielddoc"><p>The active channel is 5 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a368a574b486286c87f763957a0ef9d93" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a368a574b486286c87f763957a0ef9d93"></a>HAL_TIM_ACTIVE_CHANNEL_6&#160;</td><td class="fielddoc"><p>The active channel is 6 </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a574f72ac3bb41fe660318aa42dfdc98d" name="ggaa3fa7bcbb4707f1151ccfc90a8cf9706a574f72ac3bb41fe660318aa42dfdc98d"></a>HAL_TIM_ACTIVE_CHANNEL_CLEARED&#160;</td><td class="fielddoc"><p>All active channels cleared </p>
</td></tr>
</table>

</div>
</div>
<a id="ga1a70fcbe9952e18af5c890e216a15f34" name="ga1a70fcbe9952e18af5c890e216a15f34"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1a70fcbe9952e18af5c890e216a15f34">&#9670;&#160;</a></span>HAL_TIM_ChannelStateTypeDef</h2>

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          <td class="memname">enum <a class="el" href="#ga1a70fcbe9952e18af5c890e216a15f34">HAL_TIM_ChannelStateTypeDef</a></td>
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<p>TIM Channel States definition. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga1a70fcbe9952e18af5c890e216a15f34a430f7e41a278868bc1a7c5de6a08dc94" name="gga1a70fcbe9952e18af5c890e216a15f34a430f7e41a278868bc1a7c5de6a08dc94"></a>HAL_TIM_CHANNEL_STATE_RESET&#160;</td><td class="fielddoc"><p>TIM Channel initial state </p>
</td></tr>
<tr><td class="fieldname"><a id="gga1a70fcbe9952e18af5c890e216a15f34a38f4c5665247f7c997d0b200ed7ccc0e" name="gga1a70fcbe9952e18af5c890e216a15f34a38f4c5665247f7c997d0b200ed7ccc0e"></a>HAL_TIM_CHANNEL_STATE_READY&#160;</td><td class="fielddoc"><p>TIM Channel ready for use </p>
</td></tr>
<tr><td class="fieldname"><a id="gga1a70fcbe9952e18af5c890e216a15f34ad5dca7086716ee2cde9aaccaefd838ff" name="gga1a70fcbe9952e18af5c890e216a15f34ad5dca7086716ee2cde9aaccaefd838ff"></a>HAL_TIM_CHANNEL_STATE_BUSY&#160;</td><td class="fielddoc"><p>An internal process is ongoing on the TIM channel </p>
</td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9b87df539778a60ea940a9d5ba793f7c">&#9670;&#160;</a></span>HAL_TIM_DMABurstStateTypeDef</h2>

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          <td class="memname">enum <a class="el" href="#ga9b87df539778a60ea940a9d5ba793f7c">HAL_TIM_DMABurstStateTypeDef</a></td>
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<p>DMA Burst States definition. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga9b87df539778a60ea940a9d5ba793f7ca98c26cb59bb0c07b7f020d7ff8678bb8" name="gga9b87df539778a60ea940a9d5ba793f7ca98c26cb59bb0c07b7f020d7ff8678bb8"></a>HAL_DMA_BURST_STATE_RESET&#160;</td><td class="fielddoc"><p>DMA Burst initial state </p>
</td></tr>
<tr><td class="fieldname"><a id="gga9b87df539778a60ea940a9d5ba793f7ca44e8b59c22cd2b17d449b120e03e4952" name="gga9b87df539778a60ea940a9d5ba793f7ca44e8b59c22cd2b17d449b120e03e4952"></a>HAL_DMA_BURST_STATE_READY&#160;</td><td class="fielddoc"><p>DMA Burst ready for use </p>
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<tr><td class="fieldname"><a id="gga9b87df539778a60ea940a9d5ba793f7ca2de45462aabea1ed8b0d249441404e82" name="gga9b87df539778a60ea940a9d5ba793f7ca2de45462aabea1ed8b0d249441404e82"></a>HAL_DMA_BURST_STATE_BUSY&#160;</td><td class="fielddoc"><p>Ongoing DMA Burst </p>
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<a id="gae0994cf5970e56ca4903e9151f40010c" name="gae0994cf5970e56ca4903e9151f40010c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae0994cf5970e56ca4903e9151f40010c">&#9670;&#160;</a></span>HAL_TIM_StateTypeDef</h2>

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          <td class="memname">enum <a class="el" href="#gae0994cf5970e56ca4903e9151f40010c">HAL_TIM_StateTypeDef</a></td>
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<p>HAL State structures definition. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggae0994cf5970e56ca4903e9151f40010ca28011b79e60b74a6c55947c505c51cbc" name="ggae0994cf5970e56ca4903e9151f40010ca28011b79e60b74a6c55947c505c51cbc"></a>HAL_TIM_STATE_RESET&#160;</td><td class="fielddoc"><p>Peripheral not yet initialized or disabled </p>
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<tr><td class="fieldname"><a id="ggae0994cf5970e56ca4903e9151f40010ca4545554d7fa04d17e78d69d17cb7e4b3" name="ggae0994cf5970e56ca4903e9151f40010ca4545554d7fa04d17e78d69d17cb7e4b3"></a>HAL_TIM_STATE_READY&#160;</td><td class="fielddoc"><p>Peripheral Initialized and ready for use </p>
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<tr><td class="fieldname"><a id="ggae0994cf5970e56ca4903e9151f40010ca1ddbfef19ad0562eb8143919b710cc12" name="ggae0994cf5970e56ca4903e9151f40010ca1ddbfef19ad0562eb8143919b710cc12"></a>HAL_TIM_STATE_BUSY&#160;</td><td class="fielddoc"><p>An internal process is ongoing </p>
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<tr><td class="fieldname"><a id="ggae0994cf5970e56ca4903e9151f40010ca03e3339df71a74ac37820f72c2989371" name="ggae0994cf5970e56ca4903e9151f40010ca03e3339df71a74ac37820f72c2989371"></a>HAL_TIM_STATE_TIMEOUT&#160;</td><td class="fielddoc"><p>Timeout state </p>
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<tr><td class="fieldname"><a id="ggae0994cf5970e56ca4903e9151f40010ca318cceb243cb9ca9e01833913e4f90ea" name="ggae0994cf5970e56ca4903e9151f40010ca318cceb243cb9ca9e01833913e4f90ea"></a>HAL_TIM_STATE_ERROR&#160;</td><td class="fielddoc"><p>Reception process is ongoing </p>
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